`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    03:47:34 04/21/2013 
// Design Name: 
// Module Name:    DEPPWriter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DEPPWriter(
    input clk,
	 input reset,
    input strobeA,
    input strobeD,
    output wt,
    output [7:0] eppBus,
    input [7:0] dataIn,
    input dataReady,
    output dataWritten
    );
// Use a 3-taps shift register to synchronize EPP_strobe to our clock
wire EPP_strobe = strobeA | strobeD;  // only one is active at a time
reg [2:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[1:0], EPP_strobe};

// detect the strobe edges
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
wire EPP_strobe_edge2 = (EPP_strobe_reg[2:1]==2'b10);

// respond right away to a transaction
assign wt = strobeD ? (dataReady & EPP_strobe_reg[1]) : EPP_strobe_reg[1];

reg dataWrittenReg;
always @(posedge clk) begin
	if(reset) dataWrittenReg <= 0;
	else if(EPP_strobe_edge2 & dataReady) dataWrittenReg <= 1;
	else if(~dataReady & dataWrittenReg) dataWrittenReg <= 0;
	else dataWrittenReg <= dataWrittenReg;
	end
assign dataWritten = dataWrittenReg;
assign eppBus = strobeA ? 8'b00000000 : dataIn;

endmodule
